This invention relates generally to semiconductor device structures and methods for forming such and, more particularly, the present invention relates to using metal sulfides to improve semiconductor device structures.
The semiconductor technology trend is to fabricate small, highly integrated semiconductor electronic devices. The most common semiconductor technology presently used is based on silicon. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor field effect transistor (hereinafter referred to as xe2x80x9cMOSFETxe2x80x9d).
FIG. 1 illustrates a MOSFET 5 typically found in the prior art. MOSFET 5 includes a substrate 10 wherein a channel 14 is formed. A heavily doped source 12 and a heavily doped drain 16 are formed within substrate 10 and adjacent to channel 14 and are respectively connected to source and drain terminals (not shown). MOSFET 5 further includes a gate dielectric region 19. Dielectric region 19 includes a oxide dielectric material layer 20 with a thickness t2 positioned adjacent to channel 14 wherein a portion of oxide dielectric material layer 20 reacts with channel 14 to form a low permittivity interfacial oxide layer 18 with a thickness t1 sandwiched therebetween channel 14 and layer 20.
A gate electrode 22, which acts as a conductor to which an input signal is typically applied via a gate terminal (not shown), is formed on oxide dielectric material layer 20. Gate electrode 22 typically includes a heavily doped poly-silicon layer. Further, channel 14 is formed within substrate 10 beneath gate electrode 22 and separates source 12 and drain 16. Channel 14 is typically lightly doped with a dopant type opposite that of source 12 and drain 16.
Gate electrode 22 is physically separated from substrate 10 by gate dielectric region 19, which, in the prior art, typically includes an oxide layer such as silicon oxide (Sio), zirconium oxide (ZrO), titanium oxide (TiO), zinc oxide (ZnO), or the like. Region 19 is provided to prevent current from flowing therebetween gate electrode 22 and source 12, drain 16, and channel 14. In operation, an output voltage is typically developed between source 12 and drain 16. When an input voltage is applied to gate electrode 22, a transverse electric field is set up in channel 14. By varying the transverse electric field, it is possible to modulate the conductance of channel 14 between source 12 and drain 16. In this manner an electric field controls the current flow through channel 14.
Semiconductor devices can be used as semiconductor memories. Most semiconductor memories use an array of tiny capacitors to store data. One approach to expanding the capacity of a memory chip is to shrink the area of each capacitor. However, everything else being equal, a smaller area capacitor stores less charge, thereby making it more difficult to integrate into a useful memory device. One approach to shrinking the capacitor area is to change to a storage dielectric material with a higher permittivity.
In another related area, one concern is the thickness of the gate dielectric used in conventional complimentary metal oxide semiconductor (hereinafter referred to as xe2x80x9cCMOSxe2x80x9d) circuits. The current drive in a CMOS transistor is directly proportional to the gate capacitance. Since capacitance scales inversely with thickness, higher current drive requires continual reductions in thickness for conventional dielectrics. Present technology uses silicon oxide (SiO) based films with thicknesses near 3 nm. However projections suggest the need for 1 nm films for future small geometry devices. Silicon oxide (SiO) gate dielectrics in this thickness regime pose considerable challenges from a manufacturing perspective.
As MOSFET""s are scaled beyond the 0.1 xcexcm technology node, ultra thin silicon oxide (SiO) gate dielectrics, of less than 20 xc3x85 in thickness, exhibit significant leakage current ( greater than 1 A/cm2). In order to maintain high drive current, while minimizing leakage current, low equivalent oxide thickness is achieved by using thicker films of high permittivity gate dielectric. At these thicknesses, direct tunneling through the silicon oxide (SiO) may occur, although the effect of tunneling current on device performance may not preclude operation. Since the tunnel current depends exponentially on the dielectric thickness, small variations in process control may result in large variations in the tunnel current, possibly leading to localized reliability problems.
Silicon oxide (SiO) at these thicknesses also provides very little barrier to diffusion. Thus, the diffusion of boron (B) from doped poly-silicon gates, for example, would represent an increasingly difficult problem that might also require a move to new gate dielectrics or gate metals. The capacitance of a simple parallel plate dielectric with metal electrodes can be expressed as                               C          =                                    ϵ              ⁢                              xe2x80x83                            ⁢                              ϵ                o                            ⁢              A                        t                          ,                            (        1        )            
where xcex5 is the dielectric permittivity, xcex50 is the permittivity of free space, A is the capacitor area, and t is the dielectric thickness. In general, the increase in capacitance density (C/A) required for increasing current drive can be accomplished either by decreasing the dielectric thickness t or by increasing the dielectric permittivity xcex5 of the material. Thus, as with storage dielectrics, it is again desirable to change to a material with a higher permittivity.
The semiconductor industry has tried for several years to integrate high permittivity materials into integrated circuits. Although there has been much progress, these prior approaches each have drawbacks or limitations. One recurring problem is preventing unwanted layers from forming therebetween the substrate or first electrode and the high permittivity dielectric. Unless these layers also have a high permittivity, the overall capacitance is reduced. This can be shown clearly with an illustrative example. For this example, we will use one promising high permittivity dielectric candidate, tantalum oxide (Ta2O5) on a silicon (Si) layer. Other high permittivity dielectric materials will have different interfacial details, but will follow the same general analysis.
Tantalum oxide (Ta2O5) has a promising permittivity and reasonable band gap. However, the lower heat of formation relative to silicon dioxide (SiO2) immediately suggests that tantalum oxide (Ta2O5) is not thermodynamically stable next to silicon (Si) and will decompose to silicon dioxide (SiO2) at the interface. The capacitance of two dielectrics in series (such as a tantalum oxide (Ta2O5) dielectric layer on an interfacial silicon dioxide (SiO2) layer) is given by                                           1            C                    =                                    1                              C                1                                      +                          1                              C                2                                                    ,                            (        2        )            
where C1 and C2 are the capacitances of the two layers. From Equation 1, we can write (assuming equal area capacitors)                                           t            ϵ                    =                                                    t                1                                            ϵ                1                                      +                                          t                2                                            ϵ                2                                                    ,                            (        3        )            
where t1, t2 represent the thicknesses of the two layers, xcex51 and xcex52 represent the permittivities of the two layers, and t and xcex5 are the xe2x80x9ceffectivexe2x80x9d thickness and permittivity of the stack.
A common parameter used to describe dielectric stacks is the equivalent oxide thickness of the capacitor. This is the theoretical thickness of silicon dioxide (SiO2) that would be necessary to generate the same capacitance density as the material of interest (ignoring practical issues with thin silicon dioxide (SiO2) films such as leakage or tunneling effects). Thus,                                           t            eq                    ⁡                      (                          SiO              2                        )                          =                                            ϵ              ⁡                              (                                  SiO                  2                                )                                      ⁡                          [                                                                    t                    1                                                        ϵ                    1                                                  +                                                      t                    2                                                        ϵ                    2                                                              ]                                .                                    (        4        )            
If the interfacial layer t1 is silicon dioxide (SiO2), this equation would be rewritten as                               teq          ⁡                      (                          SiO              2                        )                          =                              t            1                    +                                                    t                2                            ⁡                              [                                                      ϵ                    ⁡                                          (                                              SiO                        2                                            )                                                                            ϵ                    2                                                  ]                                      .                                              (        5        )            
This equation shows that the equivalent (effective) oxide thickness of the stack (and hence the capacitance density) will be limited by the presence of a thin interfacial oxide. Thus, the effective oxide thickness will not be less than the thickness of the interfacial oxide. This minimum effective thickness is independent of the permittivity and thickness of the second layer.
High permittivity gate dielectrics typically used to form CMOS devices on silicon (Si) utilize transition metal oxides, such as (strontium, barium)-titanium-oxide ((Sr,Ba)TiO), (strontium, barium)-zirconium-oxide ((Sr,Ba)ZrO), (strontium-, barium)-hafnium-oxide ((Sr,Ba)HfO), or the like. Oxygen (O), however, will oxidize silicon (Si), which results in an interfacial silicon oxide (SiO) layer with a low dielectric constant. Further, the titanium (Ti) 3d state is resonant with the conduction band of silicon (Si) which results in a smaller conduction band offset. This smaller offset causes a high leakage current in CMOS devices.
Accordingly, it is an object of the present invention to provide a new and improved field effect device which can be used to form field effect devices with a lower gate leakage current.
To achieve the objects and advantages specified above and others, an improved semiconductor device which includes a sulfur-based perovskite material is disclosed. In a preferred embodiment, the semiconductor device includes a substrate with a surface and an insulating sulfur-based perovskite material layer positioned on the surface of the substrate. Further, in the preferred embodiment, a dielectric material layer is positioned on the insulating sulfur-based perovskite material layer and a gate contact region is positioned on the dielectric material layer.
In the preferred embodiment, the substrate includes silicon (Si) and the insulating sulfur-based perovskite material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a metallic sulfur-based perovskite material layer such as strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like.